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M66282FP
8192 x 8-Bit Line Memory
REJ03F0255-0200 Rev.2.00 Sep 14, 2007
Description
The M66282FP is high speed line memory that uses high performance silicon gate CMOS process technology and adopts the FIFO (First In First Out) structure consisting of 8192 words x 8 bits. The M66282FP, performing reading and writing operations at different cycles independently and asynchronously, is optimal for buffer memory to be used between equipment of different data processing speeds.
Features
* * * * * * * * Memory configuration: 8192 words x 8 bits (dynamic memory) High speed cycle: 25 ns (Min) High speed access: 18 ns (Max) Output hold: 3 ns (Min) Reading and writing operations can be completely carried out independently and asynchronously Variable length delay bit Input/output: TTL direct connection allowable Output: 3 states
Application
Digital copying machine, laser beam printer, high speed facsimile, etc.
Block Diagram
Data inputs D0 to D7
13 14 15 16 21 22 23 24
Data outputs Q0 to Q7
1 2 3 4 9 10 11 12
Input buffer
Output buffer
Read address counter
Write address counter
Read control circuit
Write control circuit
WEB 20 Write enable input WRESB 19 Write reset input WCK 17 Write clock input
VCC 18
5 REB
Read enable input
Memory array 8192 x 8 bits
6 RRESB Read reset input
8 RCK
Read clock input
7 GND
REJ03F0255-0200 Rev.2.00 Sep 14, 2007 Page 1 of 13
M66282FP
Pin Arrangement
M66282FP
Data output
Read enable input Read reset input Read clock input
Data output
Q0 Q1 Q2 Q3 REB RRESB GND RCK Q4 Q5 Q6 Q7
1 2 3 4 5 6 7 8 9 10 11 12
24 D0 23 D1 22 D2 21 D3 20 WEB 18 VCC 17 WCK 16 D4 15 D5 14 D6 13 D7
Data input
Write enable input
19 WRESB Write reset input
Write clock input
Data input
(Top view) Outline: PRSP0024GA-A (24P2Q-A)
REJ03F0255-0200 Rev.2.00 Sep 14, 2007 Page 2 of 13
M66282FP
Absolute Maximum Ratings
(Ta = 0 to 70C, unless otherwise noted)
Item Supply voltage Input voltage Output voltage Power dissipation Storage temperature Symbol VCC VI VO Pd Tstg Ratings -0.3 to +4.6 -0.3 to VCC + 0.3 -0 3 to VCC + 0 3 300 -55 to 150 Unit V V V mW C Conditions Value based on the GND pin
Recommended Operating Conditions
Item Supply voltage Supply voltage Operating temperature Symbol VCC GND Topr Min 2.7 0 Typ 3.15 0 Max 3.6 70 Unit V V C
Electrical Characteristics
(Ta = 0 to 70C, VCC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted)
Item High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage High-level input current Symbol VIH VIL VOH VOL IIH Min 2.0 VCC - 0.4 Typ Max 0.8 0.4 1.0 Unit V V V V A IOH = -4 mA IOL = 4 mA VI = VCC WEB, WRESB, WCK, REB, RRESB, RCK, D0 to D7 WEB, WRESB, WCK, REB, RRESB, RCK, D0 to D7 Test Conditions
Low-level input current
IIL
-1.0
A
VI = GND
Off-state high-level output current Off-state low-level output current Average supply current during operation Input capacitance Off-time output capacitance
lOZH IOZL ICC CI CO

5.0 -5.0 70 10 15
A A mA pF pF
Vo = VCC Vo = GND VI = VCC, GND, Output open tWCK, tRCK = 25 ns f = 1 MHz f = 1 MHz
Function
When write enable input WEB is set to "L", the contents of data inputs D0 to D7 are read in synchronization with a rising edge of write clock input WCK to perform writing operation. When this is the case, the write address counter is also incremented simultaneously. When WEB is set to "H", the writing operation is inhibited and the write address counter stops. When write reset input WRESB is set to "L", the write address counter is initialized. When read enable input REB is set to "L", the contents of memory are output to data outputs Q0 to Q7 in synchronization with a rising edge of read clock input RCK to perform reading operation. When this is the case, the read address counter is incremented simultaneously. When REB is set to "H", the reading operation is inhibited and the read address counter stops. The outputs are placed in a high impedance state. When read reset input RRESB is set to "L", the read address counter is initialized.
REJ03F0255-0200 Rev.2.00 Sep 14, 2007 Page 3 of 13
M66282FP
Switching Characteristics
(Ta = 0 to 70C, VCC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted)
Item Access time Output hold time Output enable time Output disable time tAC tOH tOEN tODIS Symbol Min 3 3 3 Typ Max 18 18 18 Unit ns ns ns ns
Timing Requirements
(Ta = 0 to 70C, VCC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted)
Item Write clock (WCK) cycle Write clock (WCK) "H" pulse width Write clock (WCK) "L" pulse width Read clock (RCK) cycle Read clock (RCK) "H" pulse width Read clock (RCK) "L" pulse width Input data setup time for WCK Input data hold time for WCK Reset setup time for WCK/RCK Reset hold time for WCK/RCK Reset non-selection setup time for WCK/RCK Reset non-selection hold time for WCK/RCK WEB setup time for WCK WEB hold time for WCK WEB non-selection setup time for WCK WEB non-selection hold time for WCK REB setup time for RCK REB hold time for RCK REB non-selection setup time for RCK REB non-selection hold time for RCK Input pulse up/down time Data hold time* Symbol tWCK tWCKH tWCKL tRCK tRCKH tRCKL tDS tDH tRESS tRESH tNRESS tNRESH tWES tWEH tNWES tNWEH tRES tREH tNRES tNREH tr, tf tH Min 25 11 11 25 11 11 7 3 7 3 7 3 7 3 7 3 7 3 7 3 Typ Max 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Notes: Perform reset operation after turning on power supply. * For 1 line access, the following conditions must be satisfied: WEB high-level period 20 ms - 8192 * tWCK - WRESB low-level period REB high-level period 20 ms - 8192 * tRCK - RRESB low-level period
REJ03F0255-0200 Rev.2.00 Sep 14, 2007 Page 4 of 13
M66282FP
Switching Characteristics Measurement Circuit
VCC RL = 1 k Qn SW1 CL = 30 pF: tAC, tOH Qn SW2 CL = 5 pF: tOEN, tODIS RL = 1 k
Input pulse level:
0 to 3 V
Input pulse up/down time: 3 ns Judging voltage Input: 1.3 V
Output: 1.3 V (However, tODlS (LZ) is judged with 10% of the output amplitude, while tODIS (HZ) is judged with 90% of the output amplitude.) Load capacitance CL includes the floating capacity of connected lines and input capacitance of probe.
Item tODIS (LZ) tODIS (HZ) tOEN (ZL) tOEN (ZH) SW1 Close Open Close Open SW2 Open Close Open Close
tODIS and tOEN Measurement Condition
3V RCK 1.3 V 1.3 V GND
3V REB GND tODIS (HZ) 90% Qn tODIS (LZ) Qn 10% 1.3 V tOEN (ZL) tOEN (ZH) VOH
1.3 V
VOL
REJ03F0255-0200 Rev.2.00 Sep 14, 2007 Page 5 of 13
M66282FP
Operation Timing
Write Cycle
n cycle n + 1 cycle n + 2 cycle Disable cycle n + 3 cycle n + 4 cycle
WCK
tWCK tWCKH tWCKL tWEH tNWES tNWEH tWES
WEB
tDS tDH
Dn
(n)
(n + 1)
(n + 2)
(n + 3)
(n + 4)
WRESB = "H"
Write Reset Cycle
n - 1 cycle n cycle Reset cycle 0 cycle 1 cycle 2 cycle
WCK
tWCK tNRESH tRESS tRESH tNRESS
WRESB
tDS tDH
Dn
(n - 1)
(n)
(0)
(1)
(2)
WEB = "L"
REJ03F0255-0200 Rev.2.00 Sep 14, 2007 Page 6 of 13
M66282FP Matters that Needs Attention when WCK Stops
n cycle n + 1 cycle n cycle Disable cycle
WCK
tWCK tNWES
WEB
tDS tDH
tDS tDH
Dn
(n)
(n)
Period for writing data (n) into memory
Period for writing data (n) into memory WRESB = "H"
Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period of n + l cycle. The writing operation is complete at the falling edge after n + l cycle. To stop reading write data at n cycle, enter WCK before the rising edge after n + l cycle. When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
REJ03F0255-0200 Rev.2.00 Sep 14, 2007 Page 7 of 13
M66282FP Read Cycle
n cycle n + 1 cycle n + 2 cycle Disable cycle n + 3 cycle n + 4 cycle
RCK
tRCK tRCKH tRCKL tREH tNRES tNREH tRES
REB
tODIS
tAC
tOEN
Qn
(n)
(n + 1)
(n + 2)
HIGH-Z
(n + 3) tOH
(n + 4)
RRESB = "H"
Read Reset Cycle
n - 1 cycle n cycle Reset cycle 0 cycle 1 cycle 2 cycle
RCK
tRCK tNRESH tRESS tRESH tNRESS
RRESB
tAC
Qn
(n - 1)
(n)
(0)
(0)
(0) tOH
(1)
(2)
REB = "L"
REJ03F0255-0200 Rev.2.00 Sep 14, 2007 Page 8 of 13
M66282FP
Variable Length Delay Bit
1 Line (8192 Bits) Delay Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK before read cycle to easily make 1 line delay.
8192 cycle 8193 cycle 8194 cycle (0') (1') (2')
0 cycle
1 cycle
2 cycle
8190 cycle 8191 cycle
WCK RCK
tRESS tRESH
WRESB RRESB
tDS tDH
tDS tDH
Dn
(0)
(1)
(2)
(8189)
(8190)
(8191)
(0')
(1')
(2')
(3')
8192 cycle
tAC
tOH
Qn
(0)
(1)
(2)
(3)
WEB, REB = "L"
n-bit Delay Bit (Reset at cycles according to the delay length)
n - 2 cycle n - 1 cycle n cycle (0') n + 1 cycle n + 2 cycle n + 3 cycle (1') (2') (3')
0 cycle
1 cycle
2 cycle
WCK RCK
tRESS tRESH
tRESS tRESH
WRESB RRESB
tDS tDH
tDS tDH
Dn
(0)
(1)
(2)
(n - 3)
(n - 2)
(n - 1)
(0')
(1')
(2')
(3')
m cycle
tAC
tOH
Qn
(0)
(1)
(2)
(3)
WEB, REB = "L"
REJ03F0255-0200 Rev.2.00 Sep 14, 2007 Page 9 of 13
M66282FP n-bit Delay 2 (Slides input timings of WRESB and RRESB at cycles according to the delay length)
0 cycle 1 cycle 2 cycle n - 2 cycle n - 1 cycle n cycle n + 1 cycle n + 2 cycle n + 3 cycle
WCK RCK
tRESS tRESH
WRESB
tRESS tRESH
RRESB
tDS tDH tDS tDH
Dn
(0)
(1)
(2)
(n - 2)
(n - 1)
(n)
(n +1)
(n +2)
(n +3)
m cycle
tAC
tOH
Qn
(0)
(1)
(2)
(3)
WEB, REB = "L" m3
n-bit Delay 3 (Slides address by disabling REB in the period according to the delay length)
n - 1 cycle n + 1 cycle n + 2 cycle n + 3 cycle
0 cycle
1 cycle
2 cycle
n cycle
WCK RCK
tRESS tRESH
WRESB RRESB
tNREH tRES
REB
tDS tDH tDS tDH
Dn
(0)
(1)
(2)
(n - 2)
(n - 1)
(n)
(n + 1)
(n + 2)
(n + 3)
m cycle HIGH-Z
tAC
tOH
Qn
(0)
(1)
(2)
(3)
WEB = "L" m3
REJ03F0255-0200 Rev.2.00 Sep 14, 2007 Page 10 of 13
M66282FP Reading Shortest n-cycle Write Data "n" (Reading side n - 1 cycle starts after the end of writing side n - 1 cycle) When the reading side n - 1 cycle starts before the end of the writing side n + l cycle, output Qn of n cycle is made invalid. In the following diagram, reading operation of n - 1 cycle is invalid.
n cycle
n + 1 cycle
n + 2 cycle
n + 3 cycle
WCK
Dn
(n)
(n +1)
(n +2)
(n +3)
n - 2 cycle
n - 1 cycle
n cycle
RCK
Qn
Invalid
(n)
Reading Longest n-cycle Write Data "n": 1 Line Delay (When writing side n-cycle <2>* starts, reading side n cycle <1>* then starts) Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle <2>* overlap each other.
n cycle <1>*
0 cycle <2>*
n cycle <2>*
WCK
Dn
(n - 1) <1>*
(n) <1>*
(0) <2>*
(n - 1) <2>*
(n) <2>*
n cycle <0>*
0 cycle <1>*
n cycle <1>*
RCK
Qn
(n - 1) <0>*
(n) <0>*
(0) <1>*
(n - 1) <1>*
(n) <1>*
Note: <0>*, <1>* and <2>* indicate value of lines.
REJ03F0255-0200 Rev.2.00 Sep 14, 2007 Page 11 of 13
M66282FP
Application Example
Sub Scan Resolution Compensation Circuit with Laplacian Filter
N n line image data
M66282 D0 to D7 Q0 to Q7
B (n + 1) line image data
x2
Adder N + K {2N - (A + B) }
1 line delay
Compensated image data
Subtractor 2N - (A + B)
xK
M66282 D0 to D7
Q0 to Q7
A (n - 1) line image data
Adder A+B
1 line delay
Sub scan direction
Main scan direction
A N B
(n - 1) line n line (n + 1) line N' = N + K { (N - A) + (N - B) } = N + K {2N - (A + B)} K: Laplacian coefficient
REJ03F0255-0200 Rev.2.00 Sep 14, 2007 Page 12 of 13
M66282FP
Package Dimensions
JEITA Package Code P-SSOP24-5.3x10.1-0.80 RENESAS Code PRSP0024GA-A Previous Code 24P2Q-A MASS[Typ.] 0.2g
24
13
HE
*1
E
F
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
1 Index mark
12
c
A2 A1
Reference Symbol
Dimension in Millimeters
*2
D
*3
e
y
bp
D E A2 A A1 bp c HE e y L
Detail F
Min Nom Max 10.0 10.1 10.2 5.2 5.3 5.4 1.8 2.1 0.1 0.2 0 0.3 0.35 0.45 0.18 0.2 0.25 0 8 7.5 7.8 8.1 0.65 0.8 0.95 0.10 0.4 0.6 0.8
A
REJ03F0255-0200 Rev.2.00 Sep 14, 2007 Page 13 of 13
L
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